A 1.8 V 64 Mb 100 MHz flexible read while write flash memory [in CMOS]
| Autor: | Joel T. Jorgensen, T. Ly, Mase J. Taub, D. Pierce, Rajesh Sundaram, Matthew Goldman, R. Kajley, G. Christensen, Saad Monasa, E. Yu, Alec W. Smidt, W. Tran, A. Sendrowski, Rezaul Haque, Bharat M. Pathak, A. Darwish, Q. Nguyen, Priya Walimbe, A. Cabrera, I. Sharif, R. Trivedi, F. Marvin, H. Shimoyoshi |
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| Rok vydání: | 2002 |
| Předmět: |
Dynamic random-access memory
business.industry Computer science Sense amplifier Registered memory Semiconductor memory Memory controller Flash memory law.invention Non-volatile memory law Computer data storage Memory architecture Bubble memory Racetrack memory Non-volatile random-access memory Memory refresh business Computer hardware Computer memory Conventional memory Flash file system |
| Zdroj: | 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177). |
| DOI: | 10.1109/isscc.2001.912420 |
| Popis: | A flash memory with flexible multi-partition architecture allows programming or erasing in one partition while reading from another partition. The 64 Mb memory uses a 0.18 /spl mu/m process that has a 0.32 /spl mu/m/sup 2/ cell. The device has 18 ns asynchronous page mode access and synchronous burst reads up to 100 MHz with zero wait state. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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