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This master thesis deals with the design of the 400GBASE-R PCS in accordance with the IEEE 802.3bs-2017 standard which defines 400 Gbps Ethernet. The first part of this thesis focuses on general architecture of FPGA and its possible variants for implementation for 400 Gbps Ethernet communication, therefore there is description of those architectures and its resources. The next part describes progression of the Ethernet and its connection to the ISO/OSI reference model. The next section of this thesis is about description of physical layer of Ethernet for 400 Gbps version, after which follows design of PCS unit and its implementation with use of resources of selected FPGA. In the last part of this thesis is description of the simulation of the implemented unit. Achieved results and outcomes of this master thesis are evaluated in a conclusion. |
