Návrh protokolu hardwarového akcelerátoru náročných výpočtů nad více jádry

Autor:	Bareš, Jan
Jazyk:	čeština
Rok vydání:	2018
Předmět:	urychlovač návrh protokolu akcelerační systém accelerator FPGA Hardware acceleration komunikační protokol communication protocol design of protocol Hardwarová akcelerace acceleration system
Druh dokumentu:	masterThesis
Popis:	This work deals with design of communication protocol for data transmission between control computer and computing cores implemented on FPGA chips. The purpose of the communication is speeding the performance demanding software algorithms of non-stream data processing by their hardware computation on accelerating system. The work defines a terminology used for protocol design and analyses current solutions of given issue. After that the work designs structure of the accelerating system and communication protocol. In the main part the work describes the implementation of the protocol in VHDL language and the simulation of implemented modules. At the end of the work the aplication of designed solution is presented along with possible extension of this work.
Databáze:	Networked Digital Library of Theses & Dissertations
Externí odkaz:	http://www.nusl.cz/ntk/nusl-376928 Zobrazit plný text záznamu