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In 1964 the first metal oxide semiconductor (MOS) integrated circuit (IC) became available. Shortly after in 1965 Gordon Moore predicted the pace of the device density increase in ICs. His prediction became a self-fulfilling prophecy, which taking advantage of the formal device scaling rules introduced by Robert Dennard in 1974, drove the evolution of the integrated electronic industry. In conventional two dimensional ICs, devices are integrated into a single layer of silicon in what is called the front end of line (FEOL) fabrication. Additional layers on top of the devices serve as inter-dielectric isolating layer and metal interconnects and are fabricated in the back end of line (BEOL) process. Scaling the dimension of devices allows for an increase in device density, improvement on device switching speed and reduction of the cost per device. The conjunction of these benefits drove the industry thus far. Over the past decade further scaling the devices while achieving also an increase in performance and cost benefits became extremely difficult. As the dimensional scaling of complementary MOS (CMOS) devices reaches its limits, three dimensional ICs (3DICs) are increasingly being considered as a path to achieve higher device densities. 3DICs offer a way to increase density by using multiple device layers on the same die, reducing the interconnect distance and allowing for a decrease in signal delay. Among different fabrication techniques, monolithic 3D integration is potentially more cost effective but requires high performance devices, a process compatible with transistor integration in the BEOL stack and needs to deliver a high device density and uniformity in order to be adopted by the very large scale integration (VLSI) industry. This work focuses on a particular laser crystallization technique to achieve monolithic device integration. The technique, called Excimer Laser Crystallization (ELC), makes use of an excimer laser to achieve a large grain polycrystalline thin-film starting from an amorphous layer, allowing integration of high quality thin-film transistors (TFTs). Thus far, the ELC technique has been studied on thin-films typically deposited on top of quartz substrate or Si/SiO₂ wafers. On the other hand state of the art VLSI integration uses more advance BEOL stacks with low-κ material as interlayer dielectrics (ILDs) to passivate the copper (Cu) interconnect lines. This thesis focuses on three different key aspect to enable laser crystallization in the BEOL for device integration: 1. Excimer laser crystallization of amorphous silicon on low-κ dielectric; 2. Excimer laser crystallization of amorphous silicon on BEOL processed wafer; 3. VLSI of TFTs on excimer laser crystallized silicon. The ELC of amorphous silicon on low-κ dielectric is first explored through one dimension (1D) finite element method (FEM) simulation of the temperature evolution during the laser exposure in two different systems: 1. amorphous silicon deposited on top of SiO₂ dielectric; 2. amorphous silicon deposited on top of low-κ dielectric. Simulations predict that is necessary a lower laser energy for crystallizing the silicon on the low-κ material. Experimental observations confirm the predicted behavior yielding a 35% lower energy for crystallization of thin-film silicon on top of a low-κ dielectric. Material characterization through defect enhanced SEM micrograph, Raman spectroscopy and XRD analysis shows an equivalent material morphology for the two system with a preferential (111) crystal orientation for the SiO₂ system. Silicon crystallization on BEOL processed wafer is studied through a combination of 1D FEM simulation and experimental observation on a silicon layer deposited on top of a SiO₂dielectric protecting the underlying damascene Cu structure. 1D FEM show that during the silicon laser exposure, because of the short pulse width of the laser (30 ns), the heat is retained in the amorphous silicon layer allowing its melting while keeping the temperature of the Cu lines below 320 °C which is a favorable condition for monolithic integration in the BEOL. Further experimental evidences show the ability of crystallizing a-Si on such structure while preserving the physical and electrical properties of the Cu lines. The feasibility of monolithic VLSI 3D integration is demonstrated through integration of TFTs devices on 200 mm silicon wafers. The integration process and performance of the TFTs device are modeled through technology computer aided design (TCAD) simulations which are used to define the process flow and the fabrication parameters. Characterization of the TFTs over multiple die yield good device performance and uniformity. TFTs characterized with 1.5 V of supply voltage have a sub-threshold slope down to 79 mV/decade, current density up to 26.3 μA/μm, a threshold voltage of 0.23 V, current On/Off ratio above 10⁵ and device field effect mobility up to 19.8 cm²/(V s) for LPCVD-sourced silicon. Furthermore, the Levinson method allows characterization of the trap density in the thin-film polysilicon devices yielding a mean value 8.13×10¹² cm². This work present an integration scheme which proves to be compatible with VLSI in the BEOL of wafers. It paves the way to further development which could lead to an high performance, cost effective, monolithic 3D integration approach useful in application such as reconfigurable logic, display, heterogeneous integration and on chip optical communications. |
