| Autor: |
Beldachi, Arash Farhadi |
| Rok vydání: |
2014 |
| Předmět: |
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| Druh dokumentu: |
Electronic Thesis or Dissertation |
| Popis: |
New Field Programmable Gate Arrays (FPGAs) are capable of implementing complete multi-core System-on-Chip (SoC) with the possibility of modifying the hardware configuration at run-time with Partial Dynamic Reconfiguration (PDR). The usage of a soft reconfigurable Network-on-Chip (NoC) to connect these cores is investigated in this thesis. At the architecture level a configurable router is proposed that supports dynamically reconfigurable networks. This router uses distributed routing for regular and irregular topologies and can vary the number of local ports and communication ports to build multi-dimensional networks with different topologies. The evaluation results show that the selection of the ideal router is different depending on traffic patterns and design objectives. Overall, the mesh network with a four local ports per router offers a higher level of performance with lower complexity compared to the traditional mesh with one local port per router. To complete this network architecture a routing algorithm is investigated capable of supporting topologies based on a variable number and size of innertorus building blocks. The inner-tori partition a traditional mesh network into an arbitrary number of sub-networks to increase the mesh performance. The subnetworks can generate irregular global topologies which are also supported by the routing algorithm. This routing algorithm supports the addition of links to the mesh topology at run-time to reduce congestion depending on the application behaviour and resource availability. The proposed routing algorithm allows the insertion of links as requested by different parts of the application without centralised control. The analysis shows that despite this dynamic behaviour the routing algorithm remains deadlock free . |
| Databáze: |
Networked Digital Library of Theses & Dissertations |
| Externí odkaz: |
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