High Performance, Real-Time, Parallel Processing Telemetry System
| Autor: | Powell, Richard L., Williamson, Gale L., Razavian, Farhand, Friedman, Paul J. |
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| Rok vydání: | 1988 |
| Druh dokumentu: | Proceedings<br />Text |
| ISSN: | 0884-5123 0074-9079 |
| Popis: | International Telemetering Conference Proceedings / October 17-20, 1988 / Riviera Hotel, Las Vegas, Nevada Flight test and signal and image processing systems have shown an increasingly voracious appetite for computer resources. Previous solutions employed special-purpose, bit-sliced technology to supplant costly general purpose computers. Although the hardware is less expensive and the throughput greater, the expense to develop or modify applications is very high. Recent parallel processor technology has increased capabilities, but the high applications development cost remains. Input/output (I/O) such as intermediate mass storage and display has been limited to transfer to general purpose or attached I/O computers. The PRO 550 Processing and Storage Subsystem of the System 500 was developed to provide linearly expandable, programmable real-time processing and an interface to distributed data acquisition subsystems. Each data acquisition subsystem can acquire data from multiple telemetry and other real-time sources. Processing resources are provided by one or more 8 MIPS (20 MFLOPS peak) processor modules, which utilize an array of predefined algorithms, algorithms specified by algebraic notation, or developed via high level languages (C and Fortran). Setup and program development occur on an external, general purpose color graphics workstation that is connected to the subsystem via an Ethernet network for command, control, and resultant data display. High-performance peripherals and processors communicate with each other via a 16-MHz broadcast bus, the MUXbus II, where any or all devices can acquire data elements called tokens. A token is a single MUXbus II word of 32 bits of data and a 16-bit tag to identify the word uniquely to the acquiring modules. The output of each device to the bus can be one or more tokens, but each device captures the bus to insert a single token. This ensures all devices receive equal priority and the MUXbus II is maximally utilized. This multiple instruction, multiple data (MIMD) architecture automatically schedules and routes data to processors or to I/O modules without control processor overhead. Traditional peripherals and administrative functions utilize the second subsystem bus, which is a traditional VMEbus. It controls the high performance devices while permitting the utilization of standard off-the-shelf controllers (e.g., magnetic tape, Ethernet, and bus controllers) for less demanding I/O tasks. A dedicated Bridge Module is the gateway for moving data between bus domains. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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