Programmable Integral / Fractional Clock Synthesizer based on Multi-phase DLL
| Autor: | WEI, SHI-JIE, 魏士傑 |
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| Rok vydání: | 2019 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 107 With the evolution of technology and the continuous improvement of the process, operating clock speed is also an important parameter to determine the digital synchronization system, In order to integrate more features, clock synthesizers are widely used in the system-on-a-chip (SoC) applications. And due to the needs of the market, clock synthesizers working at higher speeds become indispensable. In general, design techniques of clock generation can be divided into phase-locked loop (PLL) and delay-locked loop (DLL). Conventionally, clock synthesizers are often designed using PLL. However, there is no jitter accumulation in DLL. In addition, the loop filter inside DLL can be realized by a first-order capacitor with the ease of achieving system stability. The traditional clock synthesizers based on DLL can only achieve multiplication ratios of integers and one half. In this thesis, the proposed clock synthesizer using a multi-phase DLL and an edge combiner is designed and implemented in TSMC CMOS 0.18μm 1P6M process. The multi-phase delay locked loop and externally input digital signal to control the desired multiplier. and then synthesize the clock by edge synthesizer, In addition to achieving integer multiples, multiple sets of non-integer multiples can also be implemented. Input frequency range of 250MHz ~ 500MHz, can provide eight kinds of integer multiple and five kinds of non-integer multiples, frequency output frequency range 250 MHz ~ 2.5 GHz. When operating at the highest frequency, Power consumption is 40.48mW. Keywords：delay-locked loop, clock synthesizer, edge combiner |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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