Design of Low Temperature Sensitivity CMOS Relaxation Oscillator
| Autor: | MANH CUONG TRUONG, TRUONG MANH CUONG |
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| Rok vydání: | 2019 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 107 This thesis describes a self-compensated-temperature relaxation oscillator that has been fabricated in standard 0.18μm CMOS technology. The overall chip area is 563x628μm2 (including IO PADs) and the power consumption of 22.87μW at the typical corner. The proposed circuit which is capable of reducing temperature coefficient into 4.079 ppm/oC over a temperature range of 0 to 140oC with a 1.8V single power supply voltage. Consequently, this post-layout simulation result indicates that new topology can improve about 5 times compared to the previous researches. Besides, the layout strategy called common centroid generates the second-order gradient error cancellation pattern thus improving frequency output performance. Although measured temperature coefficient results of fabricated chips are under 95 ppm/oC, those chips work in proper function and have a low standard deviation of 1.71. The design is suitable as on-chip clock generations for low temperature sensitivity applications. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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