0.13 µm CMOS Digital to Analog Converter with Upsampling Interpolation Technique
| Autor: | Yang-An Lin, 林洋安 |
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| Rok vydání: | 2018 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 107 The purpose of this thesis is to implement a digital-to-analog converter with four times up-sampling technique by using interpolation. To make the digital-to-analog converter operate in high frequency, the architecture adopted is current-steering method. Before the input signal goes into the digital-to-analog converter, it will first pass through the digital-synthesis circuit with interpolative up-sampling function. This interpolative up-sampling circuit not only improves the linearity of the output, but also generates harmonics centered at the up-sampling carrier frequency and make the input signal up-sampled to the carrier frequency by its interpolative characteristic, which is the main goal of this thesis. In the layout part, this thesis splits the current source placement to reduce the mismatch of the current sources. The chip designed in this thesis is implemented in 0.13μm CMOS process. The chip size is 0.9×0.9 m"m" ^"2" and the size of current source part is 0.584×0.665 m"m" ^"2". The output swing is 0.8 V by using 1.2 V supply voltage. The measured DNL/INL are both less than 0.3 LSB, SFDR is 38 dB with 10 MHz sine wave and the total power consumption is 23 mW. In the AFDPWM (aliasing-free digital pulse width modulation ) application, the measured ACLR is -29.2 dBc when K factor is 3, frequency of PWM is 15 MHz and the bandwidth is 3 MHz, and the measured ACLR is -28.9 dBc when the signal is up-convert to 40 MHz. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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