A Probability of Error Detection Lossless Implication Selection Algorithm with Consideration of Interconnect Loading
| Autor: | Kuang-Chun Lin, 林劻錞 |
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| Rok vydání: | 2018 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 107 With the advancement of the semi-conductor manufacturing process, the feature size of transistors shrinks aggressively. The chip size could thus become smaller. However, this also makes the chip more susceptible to manufacturing defects/noises and thus more unreliable. For some mission-critical applications, such as aviation, automotive, medical electronics, if errors appear during normal operations, it may cause significant damage to human life and property safety. In the recent years, a new concurrent error detection (CED) method, called implication-based CED, has been proposed to detect errors during normal function operations of a circuit. By using the existing invariant relationships between circuit wires, particular error detection logic can be designed to improve the reliability and diagnosability of a target circuit. The implications exist not only between inputs and outputs of a logic gate, but also between wires in the circuit. One issue for the implication-based CED is that unaffordable circuit delay overhead may incur if too many implications are employed for error checking. How to select appropriate implications is thus of great importance. In this thesis, we carefully analyze the previously developed implication selection algorithm, and identify three factors that are critically related to the significance of the delay overhead. Accordingly, a systematic method is proposed to reduce the delay overhead, including selecting appropriate implications with a small size as well as inserting buffers to heavily loaded wires. By using the proposed procedure, not only the probability of error detection is guaranteed to be lossless, but also the delay overhead due to implication checking logic can be significantly reduced. In order to evaluate the effectiveness of the proposed method, 18 ISCAS’85 and ITC’99 benchmark circuits are considered for experiments. The experimental results show that our proposed method reduces 29% delay overhead on average. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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