Implementations on X-Band CMOS Quadrature Voltage Controlled Oscillator, Integer-N Phase Locked Loop and GaN High Power and High Efficiency Voltage Controlled Oscillator

Autor: Chih-Cheng Chuang, 莊志成
Rok vydání: 2019
Druh dokumentu: 學位論文 ; thesis
Popis: 107
This thesis developed four local oscillator (LO) circuits for the signal source of X band and Ka band transceivers. The X-band LO was realized in tsmcTM 0.18 μm technology. The Ka-band LO was ikplemented in tsmcTM 90 nm technology. The X-band high power and high efficiency was realized in WINTM 0.25 μm GaN process. The developed LO circuits are listed as follow, A.Implementation on X-Band Quadrature Voltage Controlled Oscillator Using Cascode Coupling Technique The circuit improves the phase noise in traditional parallel coupling technique by using cascaded-coupling topology. After measurements, the operation frequency is from 9.27 to 10.12 GHz (i.e., 8.7% tuning range). The best phase noise is -115.2 dBc/Hz at 1-MHz offset. The output power including transmission loss is -4.78 dBm. Under 1.45-V supply voltage, the power consumption is 7.72 mW which is correspondent to an FoM of -185. The chip size includes all pads is 1.096 × 0.593 mm2. B.Implementation on X-Band Integer-N Phase Locked Loop (PLL) The functional circuit blocks of the designed PLL include a voltage controlled oscillator, a current mode logic divider, a differential to single buffer, a TSPC divider, a phase and frequency detector, a charge pump, and a loop filter. This thesis analyzes the behavior model of PLL. Meanwhile, we also analyze the issue of the differential-to-single buffer amplifier. The thesis adopts the phase and frequency detector with zero dead zone topology. The PLL is locked from 9.6 to 10.05 GHz when reference signal is 37.5 to 39.2578125 MHz. The division ratio is 256 and the total power consumption is 39.2 mW. The reference spur is as low as -45.7 dBc and phase noise is -93.7 dBc/Hz at 1-MHz offset. The chip size includes all pads is 1.035 × 0.809 mm2. C.Implementation on X-Band Tunable Feedback Type Voltage Controlled Oscillator The implementation on the VCO is realized in WINTM 0.25 μm GaN process under the constraint of the via-hole at source node that makes common source topology can be only adopted. Meanwhile, no varactor model is available. After measurements, the tuning frequency is from 9.348 to 9.46 GHz, and the output power including the transmission line loss and a 30-dB attenuator is 27.89 dBm. The best phase noise is -121.62 dBc/Hz at 1-MHz offset frequency. Under the 19-V supply voltage, the total power consumption is 2204 mW. The DC-to-RF conversion efficiency is 27.89%. The FoMp and FoMposc are -195.49 and -223.38, respectively. The chip size includes all pads is 2 × 1 mm2. D.Implementation on Ka-Band Integer-N Phase Locked Loop (PLL) The functional blocks of PLL include a VCO, an injection locked frequency divider, a current mode logic divider, a differential-to-single buffer, a TSPC divider, a phase and frequency detector, a charge pump, and a loop filter. The PLL is locked from 26.52 to 27.88 GHz when reference signal is 103.6 to 108.9 MHz. The division ratio is 256 and the total power consumption is 43.9 mW. The reference spur is -48.9 dBc and phase noise is -95.8 dBc/Hz at 1-MHz offset when PLL is locked. The chip size includes all pads is 1.015 × 0.972 mm2.
Databáze: Networked Digital Library of Theses & Dissertations
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