Simulation and Device Fabrication of Poly-Si TFTs with T-shaped Gate and Air Spacers
| Autor: | Yeh, Yu-Hsiang, 葉禹翔 |
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| Rok vydání: | 2018 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 107 In this thesis, we use the Sentaurus TCAD simulation to explore the impact of the structural parameters on the electrical characteristics of T-gate devices. The effects and trade-off between using source/drain (S/D) overlapping and underlapping structures are discussed in order to find the suitable S/D implant condition for the fabrication of real devices. The influences of the gate geometry on the AC performance of the T-gate devices are also simulated. With the help of simulation, we are able to build our guidelines of making a good T-gate device. Details of the gate etching process are described and discussed. A modified process is proposed to eliminate the potential concern encountered in our previous work. Through the experiments designed and conducting on forming the T-gates, we’ve discovered that the duration of the main etching (ME) time is a key to the success of the T-gate formation. Mechanism is also proposed to explained the experimental results. Finally, characteristics of fabricated T-gate devices are presented. The structures are characterized with the TEM and the EDS technics. We also addressed the origin of the detected anonymous off-state current with TCAD simulation. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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