The Design and Implementation of a Frequency Synthesizer Based an ADPLL and Flying-Adder
| Autor: | Kuan-Wei Chen, 陳冠瑋 |
|---|---|
| Rok vydání: | 2018 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 106 The flying-adder is a digital circuit that a novel architecture is used to generate a clock signal. Its feature is fast switch. Because of mixed-signal design, combing this structure with an analog voltage control oscillator along with an analog filter will need more area and consume more power as compared to other structures. As a consequence, in this thesis an even-stage all-digital control oscillator based on the multiplexer is used to implement a flying-adder all-digital phase-locked loop. To take the advantages of wider bandwidth and small jitters, the phase detector is designed with the cyclic TDC and a Vernier delay line. The resulting flying-adder-based ADPLL can reduce the chip area, get better power efficiency, and switch rapidly in 2 cycles. The ADPLL circuit designed is implemented with the TSMC 0.18-um CMOS 1P6M cell-based library. The core area is 283 um x 281 um, and the die area is 900 um x 898 um. With NC-Verilog simulations, the output signal bandwidth is 390.7 MHz, the maximum frequency is 390.7 MHz, and the minimum frequency is 7.53 MHz. The lock time is at most 20 cycles. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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