An 8-bit Shift Register Using Double-Edge Triggered Flip-Flops
| Autor: | ANGGER BASKORO, 巴安格 |
|---|---|
| Rok vydání: | 2018 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 106 The power dissipation has become an essential issue for IC designers, which is considered a primary factor for battery-operated systems, such as a mobile phone, laptop or notebook, and some others digital devices due to the limited battery life. This thesis presents an 8-bit shift register based on a lower-power double-edge triggered (DETFF) flip-flop. In this research, the 8-bit shift register based on the low-power DETFF is carried out by using Cadence Virtuoso version 5.1 and to TSMC 0.18µm CMOS technology. The major contribution of the proposed design is a method using a double-clocking technique to latch data bits such that shorter time delay and the less power dissipation are achieved at the same time. The all-PVT-corner (process, voltage, temperature) post-layout simulation results demonstrates 35.22 mW at the highest 125 MHz clock rate. Keywords : shift register, DETFF, low power, post-layout simulation, all-PVT |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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