The Research and Implementation of Ultra High Integer Frequency Multiplier Based on Variable Shift Divider
| Autor: | Wu, ZEHI-WEI, 吳哲瑋 |
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| Rok vydání: | 2018 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 106 Nowadays, frequency synthesizer is a core element in electronic system. Two important characteristics to judge the performance of frequency synthesis system, frequency accuracy and frequency stability, respectively. Poor frequency accuracy and frequency stability lead to reduced system performance. This work proposes an architecture which was implemented and verified by both FPGA and ASIC designs. The multiplication factor of proposed frequency multiplier ranges 3 to 2^20 and the input signal range is 25Hz to 10MHz. After the chip measurements, the output frequency errors are lower than 36ppm. By using FPGA verification, the output frequency errors are lower than 5.4ppm. The proposed architecture of ultra high integer frequency multiplier consists of five modules: frequency counter, ring oscillator, variable shift divider, multi-phases generator and flying-adder frequency synthesizer. The highest multiplication factor of proposed frequency multiplier is 1048576(2^20). This architecture has been verified both by FPGA and TSMC 0.18μm process. The core circuit area is 0.07995mm^2. Furthermore, all of the elements of proposed frequency multiplier are all-digital circuits. Thus, it can speed up the ASIC design flow and verification. In this thesis, we developed an algorithm. The variable shift divider method as compared with multiplexer circuit, the multiplication factors of the frequency multiplier increased by 52428 times. For the applications of proposed architecture, we applied in four areas: a frequency stable system, correction error signal, multi-clocks generator and modulation signal generator. The signal generated by the oscillator (100MHz) through the proposed method to improve and compensates the signal accuracy and frequency drift. Thus the resolution is lower than 14.9ppb. In general, to generate or correct high-quality frequency, the signal is usually accompanied by a higher cost. However the gate count of dual-path flying adder and multi-phases generator are about 1164. In other words, we present an architecture which is also applicable to circuits require in high accuracy with low cost. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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