Low Noise Sub-Sampling Frequency Synthesizer Using a Hybrid Controlling Technique
| Autor: | Chih-Wei Liu, 劉致瑋 |
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| Rok vydání: | 2018 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 106 With the rapid development of wireless technique, the application of phase locked loop (PLL) has become an essential system to achieve frequency accuracy. Moreover; the operating frequency of wireless system has been gradually higher, the jitter becomes worse simultaneously. Hence, a low noise system has become a significant target in the future. This paper proposes a low noise sub-sampling frequency synthesizer using a hybrid controlling technique. The proposed frequency synthesizer could consider as two loop: frequency tracking loop and phase tracking loop. Take the advantage of digital circuit which has the high tolerance in process, voltage, and temperature variation as the frequency tracking path, and the sub-sampling phase tracking path operate after frequency tracking path stably. The sub-sampling phase tracking path use low frequency signal to trace high frequency signal. In that case, the phase tracking path could work without divider, therefore, the phase noise decrease 20logN(N means divisor).In addition, due to the frequency tracking path select frequency band as the coarse tuning path while minimizing effective gain, and phase tracking loop trace phase as the fine tuning path while maximizing tuning range, the phase noise decrease further more. An 8GHz integer-N PLL has been implemented by UMC 0.18um 1P6M CMOS process, the proposed frequency synthesizer provides the tuning of 7.8GHz to 8.6GHz. Phase noise is -114dBc/Hz at 1MHz offset. The power consumption of whole chip is 31.9mW. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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