Modeling and Electrical Simulation of TSV-Based 3D Package
| Autor: | Zhi-Min Zhang, 張智閔 |
|---|---|
| Rok vydání: | 2018 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 106 3D-IC evolved with the prediction of Moore''s Law, 3D-IC provides a way to improve integration, among which Through Silicon Via (TSV) is a key component, because TSV provides 3D-IC package new interconnect technology. The advantages of TSV technology include: versatile heterogeneous integration, reduced power loss, product miniaturization, and improved component performance. In this thesis, the EM simulation software (ANSYS HFSS) was used to simulate the signal transmission of the TSV model, and then the S-parameters of the TSV model were extracted. This thesis first studies the transmission signal characteristics between multiple TSVs and discusses the effects of changing the structural parameters of TSV, such as: insulation thickness, TSV diameter, height, pitch, RDL width, silicon substrate conductivity. The changing of the angle of the tapered TSV will affect the transmission signal characteristics, and the results are also compared with the cylindrical, coaxial, and irregular TSV shapes. Second, we study the S-parameter of different position of open or short defects in TSV. Open defects may occur when a bump, connecting two TSVs, is not properly realized because of an inaccurate metal filling. The short defects can be created with the expansion of the bump, RDL, during the stacking process. In second part, the S-parameter of TSV without defect is analysis as a reference; then we analyzed the S-parameter curves of TSV with open/short defects. The analysis of the effects of any position and different quantities of defects can provide a help for a non- invasive defect detection. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
| Externí odkaz: |
|