Block Control and Set Associativity Way Prediction for Low Power Cache
| Autor: | 詹詠惟 |
|---|---|
| Rok vydání: | 2018 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 106 With the improvement of process, the volume of the processor is decreasing gradually. However, the volume of the on-chip cache accounting for the processor was increasing gradually [1][2]. According to [3], the energy consumption of on-chip cache account for 45%-50% of total processor energy. Therefore, the design of cache architecture is the key of decreasing processor energy. In the set associative cache, the tag and data was accessed in parallel in order to decrease access latency. The processor requires only one data, but all tag and data in a set should be accessed. It causes the energy consumption to be wasted. Therefore, improving the access action can efficiently improve the energy consumption of cache. In this paper, we proposed two mechanisms, Dynamic Hot Set Block Control mechanism and Set Associative Place Prediction mechanism. In the first mechanism, the number of data which accessed hot set will be controlled so that the miss rate of hot set could be improved, and the wasted energy caused by cache miss can be reduced. In the second mechanism, it reduced the number of accessing data and comparing tag so that the total energy consumption of cache could be reduced. In the experiment section, we will analysis the cache miss rate and energy consumption between our proposed mechanisms and traditional cache architecture. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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