A Multiple-Mode Architecture for Fast Variable-Precision Multiplier
| Autor: | Chang,Chih-Hsiung, 張智雄 |
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| Rok vydání: | 2017 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 105 This paper presents a multi-mode variable precision fast multiplier architecture that conforms to the IEEE-754 single-precision floating-point standard. The users can adjust the architecture based on the accuracy they requested to reduce power consumption. In the architecture for variable precision, we can adjust the number of hardware components to achieve different accuracy requirement. Therefore, the architecture for variable precision has both the high-precision function and low-precision function. We can improve performance of the overall architecture by pipeline. The method is divided into two parts, including the partial product accumulation and the final addition accumulation. The main process of the architecture is the calculation and accumulation of the four independent multipliers, and the final result is acquired by the addition from final adder. Besides, the architecture has parallel computing function and the power saving mode, which can calculate two sets of low-precision data simultaneously. Finally, according to the results of the synthesis, the performance of multiplier we proposed outperforms the traditional model and improved model by 50% and 13% respectively. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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