A Study on Key Process Technologies of 4H Silicon Carbide Trench Gate Power MOSFETs
| Autor: | Tseng, Yuan-Hung, 曾元宏 |
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| Rok vydání: | 2017 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 105 As the growing demand for power saving and carbon reduction, wide bandgap semiconductor materials are vastly discussed to be the next-generation power device. With a general reduction in power loss, devices made of wide bandgap semiconductor surpass Si power devices in almost every aspects except for production cost. The ultimate goal of our research is to develop a fabrication process of 4H-SiC trench gate power MOSFET that possesses high on-state performance and good high-voltage capability. In this dissertation, several processes in fabricating a 4H-SiC trench gate power MOSFET are developed, including SiC dry etching, oxidation, LOCOS technique. We developed a two-step dry etching process that can produce an ideal U-shape trench with a vertical sidewall and rounded bottom corner. We also developed another etching recipe for the V-grooved trench that can reach different crystal faces of 4H-SiC. Oxidation mechanism of 4H-SiC in dilute N2O ambient is first established by our research group. The electrical properties of the MOS capacitors using Ar-diluted N2O oxidation are studied. The results suggest that Ar-diluted N2O oxidation could be a standard oxidation technique for gate oxide formation in 4H-SiC MOSFET. LOCOS isolation, which has been a mature technique on Si, is still not developed in 4H-SiC process. The major barrier lies in the much lower oxidation rate on SiC. However, with a pre-amorphization implantation, we have verified that LOCOS process could also be applied on 4H-SiC. The ion species dependence is studied and discussed. The SiC LOCOS process is even simpler than the Si one, but some concerns about the LOCOS oxide quality needs to be examined. The high-temperature reliability of the SiC LOCOS oxide is investigated. The impact on the MOS capacitor device when changing conventional CVD oxide to LOCOS oxide is also discussed to verify the feasibility of SiC LOCOS. As the most critical limitation, The SiO2/SiC interface quality of the gate oxide on different crystal orientations is studied. Because the conduction channel of the trench gate MOSFET is on the trench sidewall, trench MOS capacitors are fabricated to investigate the sidewall gate oxide quality. The differences between the sidewall and the planar surfaces are studied and discussed. During the development in trench gate power MOSFET, we faced various problems and challenges that would have severe influences on the device performance and reliability. These issues are addressed, and some possible solutions are also provided and verified. Our experiences are deliberately recorded and would be the foundation for future researching works. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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