Study On the Improvement of Integrated Circuit Yield by Modifying the Ion Etching Condition of Contact Window
| Autor: | Te-Chuan Huang, 黃德全 |
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| Rok vydání: | 2017 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 105 This thesis is focused on the matching of plasma power and bias power in the ion etching process for the contact and via holes prior to depositing the metal film in the semiconductor IC process. Due to the ion etching process, the accumulated charges would cause the generation of leakage current, which would further result in the yield loss of wafer. In addition to the charge accumulation issue, the native oxide is bombarded by ion etching, and then the bombarded native oxide would fall into the bottom of the contact or via holes, resulting in a re-deposition phenomenon. Owing to this unwanted issue, the step coverage of the subsequent titanium and titanium nitride deposition would become worse, resulting in the phenomenon of tungsten puncture in the metallization process of tungsten, which would be detected by the following electrical test or yield test. In order to improve the yield loss caused by the leakage current and tungsten puncture phenomenon, the matching between plasma power and bias power and the reduction of ion etching amount are adopted to minimize the cumulative charge and tungsten puncture. Experimental data shows that the adjustment of plasma power and bias power matching and the reduction of ion etching amount can achieve the purpose of reducing the leakage current to improve the yield, especially in the contact holes between the device’s electrodes and the interconnection line. However, the via holes between the interconnection lines only show little improvement. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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