Subcircuits Study of a Radar System for Object Detection
| Autor: | Ching-Fong Chen, 陳慶豐 |
|---|---|
| Rok vydání: | 2016 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 105 This thesis presents the study of subcircuits for the object-detection radar systems, including a V-band phase shifter, an application of a vendor provided modulator chip with an on-board Wilkinson power divider, and a W-band direct down-conversion receiver which consists of a low noise amplifier (LNA) and a mixer. All of the designed chips in this thesis are implemented in the TSMC 90nm CMOS process. The content of this thesis includes the design of passive devices and circuits, simuation and measurement results, conlusion and discussion. There are 6 chapters in this thesis: Chapter 1 presents the motivation of the study and the benefits of systems implemented in V-band and W-band. Chapter 2 presents the introduction of the subcircuits for radar system, including the phase shifter, the low noise amplifier and the mixer. Furthermore, this chapter presents general considerations in the designs of subcircuits of a radar system, including performance parameters for RF circuits. Chapter 3 shows the design of a V-band vector combination phase shifter. The phase shifter consists of a Lange coupler, 3 balance-to-unbalance converters (Baluns) and a vector combiner. Four signals with 90 degree phase difference, i.e. I+, I–, Q+, and Q– generated by a Lange coupler and two Baluns are input to the vector combiner. Vector combination technique is able to control the output phase by voltage. Continuous phase shift of 360 degree have been measured. The chip area is 0.732×0.948 mm2, and the power comsumption is 27.6 mW under a 1.2V supply. The range of S11 under different control voltage is from –11.88 dB to –6.63 dB. The measured P1dB is 0 dBm. The frequency range for the phase error less than 5 degree is from 62.5 GHz to 66 GHz. Chapter 4 shows the designs of a W-band direct down-conversion receiver, which cosists of a 4-stage common-source low nois amplifier and a double blanced mixer. Parallel-connected transistors and the source degeneration technique are adopted in the proposed LNA. The simulation results of S21 is 15.69 dB while the simulated noise figure is 6.66 dB. The current bleeding technique is adopted in the direct down-conversion mixer. The simulation result of the power conversion gain is 13.2 dB and the simulated noise figure is 14 dB. The whole chip size of the receiver is 1.12×0.735 mm2. The simulated power conversion gain of the receiver chain is 25.27 dB and the noise figure is 8.17 dB at 78 GHz. The 1-dB compression point is –24 dBm. The power comsumption of the proposed W-band receiver is 57 mW under a 1.2V supply. Chapter 5 presents an application of a vendor provided modulator chip and a self-designed Wilkinson divider on a PCB board. The baseband FMCW signal is up-converted to the 12 GHz band by the modulator and its power is divided by the Wilkinson divider for the transmitter and the receiver, respectively. Chapter 6 conludes the thesis and bring a short discussion. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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