0.18 µm Comparator Design and Layout
| Autor: | 黃俊穎 |
|---|---|
| Rok vydání: | 2017 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 105 This paper mainly focuses on the design of the rear end of the comparator. Comparator is by comparing the two input current or voltage of the size of the output at the output of different voltage results of electronic components. Comparators are often used in analog-to-digital conversion circuits. Somehow, the process flow is examined and drawn step by step in details. The design rules using 0.18-micron process are considered to minimize the whole layout area including active and passive devices because it is associated with the process capability. Of course, the noise is also paid attention to while placing the devices. In the end, Design Rule Check and Layout versus SPICE are used to verify the feasibility of circuit design and layout design. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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