Single-Transistor Synapse and Its Electrical model for Supervised Neural Network
| Autor: | Peng, Kang-Ming, 彭康銘 |
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| Rok vydání: | 2019 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 105 In this work, we have created a single-transistor synaptic model and demonstrated supervised learning in a silicon-based neural chip applied in pattern recognition. Each synapse in the neural circuit was implemented using analog Non-overlapped Implantation (NOI) MOSFET. This is a non-volatile memory (NVM) device capable of being implemented in a hardware artificial neural network under a supervised learning algorithm. The NOI synapse was fabricated using a 0.25 μm CMOS process but with the lightly doped drain (LDD) implantation omitted. The gate voltage of the NOI synapse serves as the neural input signal; its weight depends upon the changes in the threshold voltage due to trapped charges in the NOI synapse. The channel current represents the synapse output, defined as the product of the stored weight and applied input. The learning rate (η) was influenced by different proportions of the stress time. The NOI synapse plasticity was demonstrated using a 4×3 neural array for perceptron application. Six input patterns were used for the learning algorithm in these NOI synapses. During the training process, the output signals were supervised and compared to the target by updating the NOI synapse weights until the system converged. The experimental results from the silicon chips prove that NOI synapses have potential in the development of high-density neural network hardware. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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