A New Model for the Saturation Current of Nano-MOSFETs
| Autor: | Yu-Hao Chao, 趙御皓 |
|---|---|
| Rok vydání: | 2016 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 104 As IC industries keep making progress, the size of MOSFETs keep scaling down and their current behavior become more difficult to predict. Conventionally, the current of MOSFET is considered only due to drift current. It is believed that as the drain voltage increases continuously, and the pinch-off point will be generated which makes the total current stop increasing. The MOSFET becomes saturated. However, why does it go into saturation region instead of completely no electric current? This kind of problem attracts our attention. Speaking of current behavior, in order to describe that can find the current at the pinch-off point. Some scientists have already proposed some theories such as “velocity saturation” and “overshoot”. However, there are still a lot of problems being unable to solve by these theories. Therefore, we propose a new model based on physics to try to explain the current behavior which couldn’t be described specifically before. We add a concept of gradient of concentration to build our new model because the channel is no longer horizontal instead of gradient of concentration. That is why we make this assumption to describe the current behavior physically. In our experiments we all use the wafers which are 28nm High-K metal gate from UMC. In this thesis, the current behavior at saturation region will be focused. The diffusion current dominates at the approaching pinch-off point which is our key assumption and it has never been seen before. The final result is under our expectation; there is actually apparent diffusion current near the pitch-off point. Nevertheless, as the device is scaling, the channel length also decrease and this phenomenon will induce the larger diffusion current which can’t be ignored anymore due to the larger gradient of concentration. Therefore, a brand new model is strongly needed which is more physical than any others in the past. With our new model, IC designers can design circuits more efficiently and make the power consumption to be much lower. Also, the new model is able to testify the products in the foundry if they all follow the standards or not and to decrease the cost of development. In other words, it is a significant breakthrough for the future CMOS technology. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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