Parallel Error Correction Logic for BCH Decoder
| Autor: | MING-SHENG ZHANG, 張明聖 |
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| Rok vydání: | 2016 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 104 Conventional parallel BCH decoding algorithm is the use of a generator polynomial root into the message of the polynomial to get syndrome,then the syndrome obtained error location polynomial after which an error position Chien search algorithms and error correction information, this calculation process is quite complicated and time-consuming. Direct Decoding method is a way to calculate the error location directly determined by the received message; the message first established message location, corresponding to the relationship between the syndrome and the error location, and then use this relationship corresponds to simplify the decoding process in order to achieve better parallel decoding architecture. In this paper, we construct the (15,7,2), (15,5,3) Error location tables, and substituting the coding to verify their ability to decode. Finally, we will organize the Error location table, and with Synthesis simplisied logic gates,to facilitate future hardware implementation. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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