Design and Analysis of Nanoscale FinFET and Tunnel FET Devices for Ultra-Low-Power SRAM, Logic and Analog Applications

Autor: Chen, Yin-Nien, 陳盈年
Rok vydání: 2016
Druh dokumentu: 學位論文 ; thesis
Popis: 104
The goal of this dissertation is to provide an extensive assessment of nanoscale FinFET and TFET devices for ultra-low-power application in SRAM, logic and analog. Device-circuit interactions and co-optimizations are considered to demonstrate the advantages and concerns of these emerging devices based circuits from both the device and circuit point of view. Through our analysis, impacts of device characteristics and low-VDD operation on the leakage/delay and stability/performance of logic circuits and SRAMs, on the power/performance of analog circuits are evaluated to offer insights for both our proposed innovative circuit designs and for future low-voltage circuit designs. With superior electrostatic integrity and immune to random dopant fluctuation, FinFET device serves a promising role to replace conventional bulk MOSFET device. In addition, the possible adoption of the independent-gate control facilitates FinFET device characteristics and circuit functions. We extensively examine the stability and performance of our proposed Independently-controlled-Gate (IG) 7T FinFET SRAM cell with the conventional 6T FinFET SRAM cell and IG 6T Column-Decoupled FinFET SRAM cell. Through our analysis, our proposed IG 7T FinFET SRAM cell which exploits the independently-controlled-gate (IG) FinFET devices for reading transistor to decouple read/write paths and for access transistors to form cross-point structure provides comparable Write SNM (WSNM) and significant improvement in Read SNM (RSNM) and Half-Select SNM (HSSNM). In addition, with the 3D atomistic TCAD simulator generated Fin Line-Edge-Roughness (Fin LER) pattern, the impacts of the intrinsic device variability on the cell Read stability and Read Performance are extensively investigated. The results indicate that although the variability of independently-controlled-gate device is slightly larger compared to tied-gate device, our proposed cell provides the best μ/σ in RSNM and no Read failure events happened while other two counterparts encounter severe Read failure events due to leakage current from unselected cells flipping the storage data, revealing that our proposed cell is suitable for robust low Vmin SRAM application. Utilizing band-to-band tunneling as the major transport mechanism, Tunnel FET (TFET) device with capability to surmount the thermionic limitation and to provide superior switching characteristics is regarded as the potential candidate for ultra-low voltage digital applications. Through our comprehensive analysis of the TFET device characteristics, it is found that the pronounced Miller capacitance (CGD) in TFET device undermines the steep-slope advantages and degrades both the switching delay and switching energy. The impacts of several device designs including the Dual Oxide (DOX), Drain-Side Underlap (Dund) and Dual Metal Work Function (DWF) on mitigating the Miller capacitance while maintain the switching characteristics of TFET device are comprehensively investigated and compared. Our results indicate that TFET device with DOX design provides superior reduction in Cinv and C¬gd while retaining comparable Ion-Ioff characteristics among the three design techniques. On the other hand, to enable MOSFET devices for high-speed low-power operation with extensively reduced supply voltage, advanced assist-circuit such as using the dual-supply dual-VT technique is indispensable at the cost of more complicated assist-circuits and needs of on-chip level shifter to generate dual supplies. We use TCAD mixed-mode simulations to comprehensively investigate the feasibility of sub-0.2V high-speed low-power circuits with the four topologies, nominal MOSFET-based circuits, MOSFET-based circuit with dual supply, dual-VT assisted circuits, nominal TFET-based circuits and TFET-based circuits with DOX design. The delay, dynamic energy, and Standby power of the logic circuits including NAND, Inverter, BUS Driver and Latch are comprehensively analyzed and compared. The results indicate that DOX TFET would be the best candidate in considering both the energy-delay product (EDP) and leakage power for NAND, Inverter and Latch circuits. While for Bus Driver in which the largest delay would take place among all logic blocks investigated, both the nominal and DOX TFET-based circuits outperform the nominal MOSFET-based circuits in EDP by about two orders of magnitude and consume comparable Standby power, revealing the potential of TFET device to achieve high-speed low-power circuit operation at VDD = 0.2V. In addition to logic circuits, various TFET SRAM cells including conventional 7T/8T SRAM cell, 6T SRAM cell with assisted footer and our proposed cells to circumvent the difficulties implementing TFET with conventional 6T SRAM topology are statistically examined and compared. The results indicate that our proposed 7T Drive-Less (DL) TFET SRAM cell with the utilization of 4T DL SRAM as the basis along with the independent gate control can effectively improve the stability of the bit cell in Hold, Read and Write mode with adequate bit cell area compared with other counterparts. On the other hand, with the process compatibility in TFET and CMOS device fabrication, we propose a mixed TFET-MOSFET 8T SRAM cell to exploit merits of both TFET and MOSFET devices. The detailed analysis on stability, performance and effectiveness of using different write-assist schemes are extensively demonstrated. Through our comprehensive study, our proposed mixed TFET-MOSFET 8T SRAM cell provides significant improvement in stability, performance and Vmin, exhibiting the chance to stand for robust ultra-low power SRAM design at the cost of slightly larger bit cell area. The advantages of the TFET devices for analog applications are assessed to examine the potential for SoC applications. The detailed analog properties and the figure-of-merit (FOM) of TFET and FinFET devices including the transconductance (gm), output resistance (Ro), intrinsic gain (gm x Ro), intrinsic capacitance and linearity are comprehensively studied from intrinsic device physics point of view. Our analysis indicates that for cost-performance ultra-low voltage/power applications, TFET provides substantial merits in intrinsic gain compared with the FinFET device while for high-performance applications, FinFET device outperforms the TFET device at moderate and high voltages. Besides, the operational transconductance amplifier is taken as the fundamental block to investigate the opportunities and concerns of the TFET device for analog/mixed-signal circuit applications. The results indicate that for cost-performance ultra-low power application, TFET OTA provides more than two times higher unity-gain frequency (fT), and 10dB larger common-mode rejection ratio (CMRR) than FinFET OTA at comparable power consumption design. As the continual scaling of device dimension along with the reduced supply voltages, the impacts of intrinsic device variations become the critical concerns affecting device characteristics and circuit designs. The in-depth assessment of the impacts of Work-Function Variation and Fin Line-Edge Roughness on TFET and FinFET device characteristics are carried out through atomistic 3D TCAD simulations. Look-up table based Verilog-A model calibrated with TCAD results is built for each variation source and incorporates with HSPICE simulations to efficiently investigate impacts of Work-Function Variation and Fin Line-Edge Roughness on TFET SRAMs including our proposed mixed TFET-MOSFET 8T SRAM cell, conventional FinFET 8T SRAM cell and TFET 8T SRAM cell. For the first time, the feasibility/issues of each SRAM cell for ultra-low voltage operation considering intrinsic device variability are addressed. Our results indicate that our proposed mixed cell with exploiting merits of both devices provides superior stability and insusceptibility to intrinsic device variations, revealing its viability and robustness to operate at ultra-low voltages.
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