A 3D Memory Wafer To Wafer Stacking Algorithm
| Autor: | Rui Mao, 毛睿 |
|---|---|
| Rok vydání: | 2014 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 102 As the process technology continues to evolve, IC become smaller and high performance, and the cost become higher. A 3D-IC uses Through Silicon Via (TSV) is an emerging technology, higher performance, and lower power consumption compared to planar ICs. However stacking yield is a problem of 3D-IC. In this thesis, we propose a new algorithm using improved from the hungarian method of assignment on the three-dimensional memory for wafer to wafer stacking. Our results show that our algorithm can be a reasonable amount of time, given the higher stacking yield. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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