Design of CMOS voltage-to-time converter for CM/DM analog-to-digital conversion
| Autor: | Shih-hao Ou, 歐士豪 |
|---|---|
| Rok vydání: | 2013 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 102 With advances in integrated circuit (IC) processing technology, medical devices are becoming miniature, with low power consumption. Therefore, wearable and implantable applications become feasible, and patients can conveniently monitor their own health parameters. The analog-to-digital converter (ADC) is a crucial building block in such systems, providing the interface between the analog input signals and the digital domain used for signal processing in the microprocessor and by software used to monitor the instrument output. In this thesis, a pair of single-slope integrating ADCs is designed and tested, providing two 8-bit output channels. The ADC channels can be paired on-chip to provide a differential-mode (DM) and common-mode (CM) signal output. The conversion circuit consists of a bias generator, a voltage-to-time converter with comparator, and the digital CM/DM output circuits. The main focus of this thesis is on the design of the voltage-to-time converter circuit and its supporting blocks. Test chips are realized in TSMC 0.35 µm process technology with an active area of 726 μm × 630 μm. The reported measurement results show a power consumption of 41μW, a maximum conversion rate of 11.5 kS/s, differential non-linearity (DNL) below 1 LSB, integral non-linearity (INL) below 1.02 LSB, and a figure-of-merit (FOM) of 19.7 pJ/step, making the design suitable for low-power biomedical application. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
| Externí odkaz: |
|