A Reconfigurable Cache for Efficient Usage of the Tag RAM Space
| Autor: | Yun-Chung Yang, 楊允中 |
|---|---|
| Rok vydání: | 2014 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 102 In almost every typical SoCs (System-on-Chip) in modern days, the size of cache grows larger as new SoC fabrics enhanced to satisfy the variety of workloads. Cache occupies the whole chip area more than 60% in SoC. Most of the time, application does not use the entire cache space. Consequently, the underutilized cache space consume a certain power constantly without any contribution. Thus, some of the industry company in present day, starting to develop mechanisms to make the cache size reconfigurable. In recent work, an idea of scratchpad memory extends the turned-off part of cache space as local memory, also called SPM (scratchpad memory), which can benefit other activities to further increase the performance or enhance instruction delivery. However, SPM only uses the part of data RAMs, the tag RAMs part is still remaining un-used. In this work, we proposed an architecture that can exploit the SPM space by reusing tag RAMs in either instruction or data cache. Implementing the proposed architecture on an ARM compatible CPU data cache for case study. The experiment results show that we can reclaim 12.5% of memory space with 0.08% hardware overhead in the configuration of 4KB, 4 way-associative cache with 32 byte line size which is equivalent to ARM Cortex-A5. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
| Externí odkaz: |
|