Chip Design of Dual-Mode Modified Step-by-StepReed-Solomon Decoder
| Autor: | Yu-Shan Su, 蘇郁善 |
|---|---|
| Rok vydání: | 2013 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 101 Providing the capability of excellent recovery data suffered from random and burst errors, Reed-Solomon codes (RS) have been widely used in various wireless communication and multimedia video systems. Step-by-step algorithms, a kind of originally decoding method which is suited for Bose-Chaudhuri-Hocqyenghem (BCH) codes, can simultaneously determine the error locations and their corresponding error values for high speed decoding. However, the clock cycle time and power consumption of this method is too high for non-binary Reed-Solomon codes. The modified step-by-step algorithm, therefore, was proposed to reduce the foregoing issues at the hardware complexity and power consumption. In this Thesis, based on the modified step-by-step decoding and Gaussian elimination algorithms, this work proposed two RS(255, 239) and RS(204, 188) Reed-Solomon hardware architectures, and then proposed a dual-mode Reed-Solomon decoder that is a version of the combination of two previous designs. Furthermore, because the step-by-step decoding method must calculate the determinant of syndrome matrices first, the proposed architecture performed Gaussian elimination using a 1-D systolic array for reducing the hardware complexity and power consumption instead of a 2-D systolic array. Finally, using 0.18 μm CMOS technology, the proposed chip has a working frequency up to 166MHz according to the static timing analysis of post-layout simulation. The gate counts and power consumption of the chip core are approximately 32K gates and 57 mW at 166MHz. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
| Externí odkaz: |
|