High-Speed and Area-Minimized FIR Filter Design using Memory-Based Multiplication on FPGAs
| Autor: | Hsu, Jin-Wei, 許晉維 |
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| Rok vydání: | 2012 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 101 The complexity of finite impulse response (FIR) filters is dominated by multiple constant multiplication (MCM) block which realizes the multiplication of one data sample with multiple constant coefficients. Many works have been proposed for minimizing memory size since multiplications in an MCM block can be implemented by memory-based multipliers. In this work, we present an integer linear programming (ILP) based approach to minimize the area of MCM block implemented on the field programmable gate array (FPGA) by finding the minimal number of common partial products to carry out all constant multiplications. Experimental results show that on average, compared with an existing state-of-the-art method, the proposed method reduces delay and area by more than 10% and 50%, respectively. Moreover, the reduction of memory size is more prominent when the number of constant coefficients increases. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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