Dynamic-Performance-Improved Techniques for Nyquist-Rate Current-Steering DACs
| Autor: | Wei-TeLin, 林韋德 |
|---|---|
| Rok vydání: | 2013 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 101 Current-Steering Digital-to-Analog Converters (DACs) are widely used in high–speed applications. In this dissertation, several dynamic-performance-improved techniques for Nyquist-rate current-steering DACs are presented. For low-cost DAC designs, a DEM method, random rotation-based binary-weighted selection (RRBS), is proposed which offers the circuit simplicity that using binary- weighted coding and greatly reduces the mismatch effect. Compared with the conventional binary-weighted architecture, the switching activity of RRBS is improved and the glitch energy issues are inherently reduced by randomization. Although its switching activity is not near-minimum, the binary-to-thermometer decoder is not required, thereby further saving chip area. A 10-bit RRBS DAC is implemented with only 0.034 mm2 in a 0.18μm CMOS process. Measured performance achieves 〉61 dB spurious-free dynamic range (SFDR) in the Nyquist bandwidth with 500 MS/s, while its active area is less than one-tenth of that required by state-of-the-art 10-bit current steering DACs. Its SFDR is also comparable to that of 12-bit published designs. Three popular figures-of-merit (FoMs) are used to compare this design with other state-of-the-art 10~12-bit DACs, with the proposed design performing best with 2 FoMs. For high-resolution DACs, A novel layout pattern, i.e., one-line-routing (OLR), incorporating with DEM method for low-cost current-steering DACs is proposed. The proposed OLR method exhibits good gradient error compensation with low complexity and small metal routing overhead compared with most published methods, and induces less parasitic capacitance. With the proposed OLR incorporating with DEM, a 14-bit current-steering DAC is implemented in a 0.18μm CMOS process. The measured SFDR exceeds 80 dB at low output frequency and maintains 70 dB at near Nyquist output frequency clocked at 300 MS/s. The DAC has an active area of less than 0.18 mm2, which achieves a smaller active area than most of the state-of-the-art 14-bit DACs. For high-speed, high-resolution DACs, a technique utilizing dynamic-element- matching and digital return-to-zero, called DEMDRZ, is proposed to simultaneously suppress the mismatch- and transient-induced nonlinearity. In doing so, the usage of small-sized current sources and switches is possible, and the spurious-free dynamic range (SFDR) and third-order intermodulation distortion (IM3) for high signal frequencies can be improved. A 12-bit compact, low-power, high-speed, DAC is implemented in TSMC 40nm CMOS process. The implemented DAC achieves 〉70 dB SFDR for signals over the 800 MHz Nyquist bandwidth at 1.6 GS/s and 〈 -61 dB IM3 for signals over the 1.4 GHz Nyquist bandwidth at 2.8 GS/s. Further, it dissipates 40 mW with a single 1.2 V supply. The active area of the DAC is 0.016 mm2, which is less than 6% of other state-of-the-art 12-bit current steering DACs. Furthermore, the implemented DAC performs best with three common figure-of-merits (FoMs). |
| Databáze: | Networked Digital Library of Theses & Dissertations |
| Externí odkaz: |
|