Design of CMOS Image Sensor Digital Analog-Front-End Circuits
| Autor: | Chien-Ting Li, 黎建廷 |
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| Rok vydání: | 2013 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 101 This thesis presents design of a 10-bit CMOS image sensor analog front-end (AFE) circuit. The front-end circuit consists of a photodiode array of 256, a three-time sening amplification circuit for each photodiode, and a 10-bit pipelined analog-to-digital converter (ADC) as readout circuit. Among the CMOS image sensor architectures, the active type is the most popular compared to the passive one. The active CMOS image sensors has higher sensitivity, lower power consumption, and is highly integrated. In addition, use of the pipelined ADC can achieve moderate resolution for higher speed applications such as image processing. This thesis compares three kinds of CMOS image AFE circuits to obtain the best architecture among them. The TSMC 0.18 um, 1P/6M, mixed-signal/RF, 1.8V/3.3V process is used for design. HSPICE simulation results show that, the architecture with a CMOS image sensor array of 64 by 4 and four 10-bit pipelined ADCs has the best result for area and power consumption. With a sampling frequency of 64MHz and input frequency of 19.53125KHz and the SFDR is 50dB and the power consumption is 312mA. The total chip area is estimated to be 4.381mm. The future work is to enhance the speed, to reduce the circuit area, the supply voltage, and the power consumption. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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