Study of Nano-scale Shallow Trench Isolation Planarization Process for Semiconductor Integrated Circuits Manufacture
| Autor: | Huang, Kuo-Feng, 黃國峰 |
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| Rok vydání: | 2012 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 100 With semiconductor manufacture shrunk down to the nano-scale technology, the shallow trench isolation (STI) of the device would be faced to the nano-scale manufacturing and integration. The nano-scale shallow trench isolation could provide well isolation and surface condition to reduce current leakage. The well shallow trench isolation performance was dominated by the Oxide film deposition and following Chemical Mechanical Planarization (CMP). Accompanying device dimension shrunk down, the semiconductor manufacture micro defect issue, such as silicon substrate damage due to Nitride film not stopping the polishing planarization effectively, or device current leakage induced by micro scratch. This thesis would focus on the slurry effect on micro defect including silicon damage and micro scratch. Unique high SiO2/ Nitride removal rate selectivity slurry and combining new concept STI polishing sequence to two steps from three steps could purpose well isolation and surface condition. It also results in well device leakage performance on nano-scale semiconductor manufacture. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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