Robustness of Nano-Scale SRAM Design: Reliability and Tolerance Techniques
| Autor: | Yang, Hao-I, 楊皓義 |
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| Rok vydání: | 2011 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 100 This thesis discusses the reliability and tolerance techniques for the robust nanoscale SRAM design. It provides comprehensive analyses on the impacts of Bias Temperature Instability (BTI) and gate-oxide breakdown on power-gated SRAMs, including the stability and Write-ability of cells, Read/Write access paths, replica timing control circuits, and the data-retention power-gating devices. We show that the degradation of power-gating switches induced by BTI or gate-oxide breakdown significantly affects the stability of SRAM arrays. The degradation of timing control circuits caused by BTI results in SRAM performance decreasing. Moreover, based on these analyses, the degradation tolerance techniques are also presented. We provide the dual gate-oxide thickness power-switch to improve the time-to-dielectric-breakdown (TBD) of the power-switch while maintaining the performance without side effect. We also present some techniques to mitigate SRAM degradation induced by BTI, including dual-VTH cells, and the banking data-retention power-gating technique to reduce the stress voltage during Standby mode. Furthermore, a low VMIN disturb-free 8T SRAM cell with cross-point Write structure and adaptive VVSS control is introduced. The Monte Carlo simulation results show that the proposed 8T cell improve Static Noise Margin about 120% comparing with the conventional 6T cell. A 512Kb test chip is implemented in UMC 55nm Standard Performance (SP) CMOS technology, and the chip area is 1100.3×1434.50 um2. The measurement results demonstrate operating frequency of 1.143GHz at 1.5V, 943MHz at 1.2V, and 209MHz at 0.6V. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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