Design of 5-Gb/s and 10-Gb/s CMOS Optical Receiver Front-Ends
| Autor: | Shun-Liang Yang, 楊舜量 |
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| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 100 In this thesis, we design a transimpedance amplifier (TIA) and two high-speed optical receiver front-end circuits for the receiver of an optical-fiber communication system. These chips are designed in 0.18μm CMOS technology. The first chip is a TIA designed to operate at 5-Gb/s data rate. The second chip is designed to combine the TIA with limiting amplifier (LA), and its operating rate is 5-Gb/s. The third circuit is an optical receiver front-end circuit designed to operate at 10-Gb/s data rate. The input stages of the proposed TIAs are designed using regulated cascade (RGC) circuit. The first TIA uses a conventional cascaded third-order gain stage, and it exhibits the transimpedance gain of 53.5 dBΩ, the bandwidth of 4.1 GHz, and the power dissipation of 59.4 mW. The LA of the second chip uses three cascaded third-order gain stages with interleaving active feedback, and it exhibits the transimpedance gain of 56.9 dBΩ, the bandwidth of 5.05 GHz, and the power dissipation of 82.8 mW. The third circuit adds the offset cancellation circuit with fT doubler buffer, and it exhibits the transimpedance gain of 92.1 dBΩ, the bandwidth of 8.01 GHz, and the power dissipation of 264 mW. In this thesis, the transimpedance amplifier and limiting amplifier are integrated into one chip. The chip can avoid external interference, enhance the circuit’s performance, and cost down. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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