The IP Core Design Of The SuperSpeed Universal Serial Bus
| Autor: | Hong, Yihao, 洪義豪 |
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| Rok vydání: | 2012 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 100 Universal Serial Bus (USB) with plug-and-play and hot-swap functions is one of today's high-speed transmission interface products. In addition, the USB3.0 5Gbps high-speed transmission with cheap price makes the USB 3.0 become a popular electronic device. In order to thoroughly understand the structure of the USB3.0, the silicon intellectual property (Silicon IP) design of high speed USB 3.0 using Verilog hardware description language (Verilog-HDL) is focused in this thesis. The USB3.0 contains three layers including physical layer, link layer and protocol layer. The hardware implementation of the main modules in the physical layer contains the 8B/10B edge decoder, serial-to-parallel conversion circuit, the scrambling device reconciliation frequency ... and so on. Furthermore, the implementation demonstrates the functionality of the USB3.0 link layer and protocol layer architecture within the link layer using the state machine of LTSSM (Link Training & Status State Machine) for data communication, including the formulation of the packet link control and management, instruction control flow through the link layer. Finally, the USB3.0 IP core is verified using FPGA implementation. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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