High-Speed Timing Generator using Dual Delay-Locked Loop
| Autor: | Jia-Xing Chen, 陳嘉興 |
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| Rok vydání: | 2011 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 99 Timing generator is widely used in automated test equipment, integrated circuit process with continuous improvement has entered GHz operating frequency range, in order to improve IC testing frequency and accuracy, timing generator to provide higher operating speed and high precision timing trigger signal, to give control of the chip and test equipment test data between the comparison. This paper is the use of delay-locked loop (DLL) circuit architecture, dual-loop delay-locked loop to show high precision and low jitter of timing signal, which double-loop timing generator includes coarse and fine level timing generator, and has dynamic adjustment control can switch timing output. Coarse timing generator is composed of a conventional delay-locked loop; fine timing generator in the voltage-controlled delay line (VCDL) to join phase interpolation method to show, equipped with dynamic adjustment control can switch at any time In order to avoid harmonic locking and lock error, then with a broad-band external modulation control, can switch the operating band voltage-controlled delay line to suppress. This circuit uses TSMC CMOS 0.18μm 1P6M of the chip design process, using circuit simulation software analysis, design resolution for the TT 25 o C 9.77ps 800MHz, the input operating frequency of 600M ~ 900MHz, the output peak to peak jitter of 4.43ps, INL ( LSB) -0.38 ~ +0.27; DNL (LSB) -0.37 ~ +0.29. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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