A Chip-Package-Board Codesign Methodology
| Autor: | Hsu-Chieh Lee, 李緒頡 |
|---|---|
| Rok vydání: | 2011 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 99 In today''s IC production, the design processes of chip, package, and board are separate from each other. However, the lack of information from other domains dramatically increases the design difficulty and reduces the quality of the product. Especially, while most current IC''s still resides on a Printed Circuit Board (PCB), the PCB is usually not considered during the design of chip and package, which makes the PCB routing very difficult to complete with satisfying quality. As a result, PCB routing often becomes the bottleneck of the whole design flow, which significantly lengthens the time to market and reduces the profit margin. In this thesis, we provide an extensive survey about the previous works on flip-chip RDL routing and PCB escape routing. We systematically introduce the methods and analyze their strengths and weaknesses in detail. After that, we propose a chip-package-board codesign methodology that provides cross-domain information integration. Our codesign flow has four major procedures: (1) inverse escape routing for board signal-ball assignment, (2) package aware I/O placement that reduces the RDL routing congestion, (3) RDL bump reassignment that balances the routing congestion of RDL and board, and (4) RDL and escape routing that completes the flow. Experimental results show that our codesign flow successfully complete the routing for all test cases while the traditional flow and other two board-driven flows all fail at either RDL routing or PCB escape routing. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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