CMOS Circuits and Architecture Design Techniques for Sub-3GHz Wireless Harmonic Rejection Receiver
| Autor: | Hua-Chin Lee, 李華錦 |
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| Rok vydání: | 2011 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 99 Modern wireless data communication has been in the demand for various applications and di¤erent wireless communication standards. In order to increase data rate for data transmission, choice of utilizing wide bandwidth is much easier than enhancing channel capacity through the signal-to-noise ratio. Therefore, exploring new techniques to use wide bandwidth plays an important role in the future wireless communication systems. However, to e¢ ciently use the desired frequency spectrum, the cognitive radio (CR) systems are proposed to solve this issue. This system has capability to sense the environment variances, and dynamically adjusts its bandwidth, modulation, power, and other parameters, in order to achieve optimal performances and maximum transmission rate. The dissertation takes the cognitive radio system on TV bands and UNII bands as the reference to discuss the circuits and architecture design of the wideband wireless receiver. A wideband direct-conversion (DC) harmonic-rejection (HR) receiver front-end with built-in switched-load PLL-based frequency synthesizer is proposed and validated with measurements for cognitive radio standard and systems. The direct-conversion harmonic-rejection (DCHR) receiver consists of a broadband gm-boosted high dynamic range noise-cancelling low-noise ampli.er (LNA), an 8-phase switching mixer array, a two-stage cascaded HR low-pass filter and an 8-phase switched-load PLL-based frequency synthesizer. Realized in a 90-nm 1P9M digital CMOS technology with an active area of 1x1 mm2, the DCHR receiver achieves a 34 dB conversion gain, 50 dB and 53 dB of 3rd and 5th harmonic rejection respectively without any o¤-chip RF filtering. The measured minimum receiver noise .gure (NF) is 3:5 dB, and the average measured NF is 4 dB within the entire 3 dB bandwidth. Furthermore, the IIP3 is -10 dBm from 100MHz to 1:2 GHz with 5MHz tone spacing. The total power consumption is 28:6mW with embedded LNA, switching mixer, HR low-pass filter and frequency synthesizer under 1 V supply operation. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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