CMOS Analog Front-end Transceiver IC for Wireline Communications
| Autor: | Kao, Min-Sheng, 高旻聖 |
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| Rok vydání: | 2011 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 99 This study proposes several circuit design techniques to achieve high performance CMOS transceiver chipset for wire-line communication. The circuit concepts are demonstrated by a 20-Gb/s CMOS 0.13-μm laser/modulator driver design and a 10-Gb/s CMOS 0.18-μm limiting amplifier design. The performance evaluation are as good as the advanced expensive III-V compound technology and the fabricated CMOS circuits are suitable for further integration with SERDES, CDR, and CODEC ICs for wire-line communication due to the small die size and low power consumption. The proposed 20-Gb/s laser/modulator driver is fabricated in 0.13-µm mixed-signal 1.2/2.5V 1P8M CMOS process. This work consists of a shunt-series inductor peaking pre-driver stage and a pre-emphasis output driver stage with source de-generation configuration including inductive local feedback network to enhance the operation bandwidth. The data rate is measured up to 20-Gb/s with 3.5VPP S.E. output amplitude in driving 50-Ω output load when the input amplitude is less than 0.15VPP and the rise/fall time of output waveform is less than 22-ps. The total power consumption is 900-mW with 1.2/4.0V dual supply and the chip die size is 900×800-µm2. The proposed 10-Gb/s current mode logic (CML) limiting amplifier is fabricated in 0.18-µm 1P6M CMOS process. This work consists of input equalizer, CML output buffer and gain stages with active-load inductive peaking, duty cycle correction (DCC) and gain control features. The circuit techniques include active load inductive peaking, source de-generation peaking and active feedback with current buffer in Cherry-Hooper topology to enhance operation bandwidth. The proposed design provides 600-mVpp differential voltage swing in driving 50-Ω output loads, 40-dB input dynamic range, 40-dB voltage gain and 8-mVpp input sensitivity. The total power consumption is 85-mW with 1.8V supply and the chip die size is 700×400-µm2. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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