Optimization Methods for Modern Lithography and 3D Integration Technologies
| Autor: | Tsai, Ming-Chao, 蔡名詔 |
|---|---|
| Rok vydání: | 2010 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 99 As the semiconductor technology advances, the interconnect delay gradually dominates the entire circuit delay and becomes the bottleneck of the circuit performance. To further improve the performance, manufacturers invest great deal of effort to reduce the delay by miniaturizing the chip size and shortening the interconnects. In this dissertation, we propose using modern lithography and 3D integration technologies to scaling down the chip size. Since the phase shift mask(PSM) is a very effective lithography technology to miniature the layout patterns, we focus on PSM design issues and propose a wire spreading algorithms to modify layouts for PSM compliance. Experimental result shows that our algorithm can eliminate more than 98% of phase conflicts without increasing the die size. With the aid of through-silicon via (TSV), 3D integration is able to shorten the wirelength of inter-tier net and achieves high performance. However, TSV is not volumeless point and cannot be placed anywhere on a layout. Without planning TSVs in the early design stage, a post TSV insertion procedure is required to arrange TSV to white space. To this end, we also propose a 3D floorplanning algorithm to simultaneously plan functional blocks and TSVs. Experimental results show that our algorithm outperforms a post-processing TSV planning algorithm in wirelength by 22.3%. Although TSV potentially reduces the wirelength of a 3D-IC, the area overhead of TSV poses negative impact to circuit. Applying too many TSVs in a design increases the size of a 3D-IC and extends the distances among active devices. Therefore, we also propose evaluation methods to study the trade-off among wirelength, number of TSVs, size of TSVs and placement of 3D-ICs. Experimental results reveal that the optimal number of TSVs of a design varies with the size of TSVs. When the size of TSV is small, the using more TSVs is beneficial for wirelength reduction. On the contrary, when large TSV is applied, a design prefers using routing topologies with least number of TSVs to minimize the total wirelength. Also, our experimental results show that the best partition scheme for placement is sensitive to the size of TSV. The larger TSV we use, the earlier we have to partition cells to different tiers. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
| Externí odkaz: |
|