Structural Evaluation of Wafer Level Chip Scale Package by Board Level Reliability Tests
| Autor: | Li-Cheng Lin, 林豊誠 |
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| Rok vydání: | 2011 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 99 The Wafer Level Chip Scale Package (WLCSP) is gaining popularity for its performance and ability to meet the miniaturization requirements of portable consumer electronics, such as cell phones. For the industry of electronic package, the package life of electronic products is deemed as the essential consideration in the operation period. In practice, electronic products are usually damaged due to a harsh mechanical impact, such as drop and bending. The solder interconnections provide not only the electronic path between electric components and printing circuit board, but also the mechanical support of components on the printing circuit board, so that the reliability of solder interconnection becomes an essential consideration for a package. In the thesis several parameters, including redistribution layer (RDL) material and thickness, passivation material and thickness, under-bump metallization (UBM) structure factors are discussed. A variety of WLCSP structures are investigated for solder joint reliability performance. In addition to the fatigue lives of the test vehicle, locations and modes of fractured solder joints were observed. It was found that wafer level packaging structure under drop clearly related with the characteristic life. The weakest point of solder ball was intermetallic compound (IMC), and wafer level packaging structure was the crack into the second passivation layer and UBM interface of the corner. WLCSP under temperature cycling test was done and observed the fracture only occurred at the solder ball near the package. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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