Design and Implementation of High-Speed Multi-operand Decimal Adders
| Autor: | Hsin-Hao Peng, 彭信豪 |
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| Rok vydání: | 2011 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 99 In this paper, we have proposed area-efficient decimal adders with three inputs. By using proposed analyzer circuits and the generation of correction terms with recursive schemes, our proposed decimal adders could perform efficient summations with three inputs of operands. Synthesis shows that our proposed adders save up to 41.6 % area cost compared to previously reported decimal adders with three inputs under the same delay constraint. Besides that, the power consumptions for our decimal adders are lesser. Our proposed decimal adders could be applied to ease the tremendous computation efforts for decimal numbers. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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