Design and Implementation of K-band and V-band Chip Antenna and Related Circuit
| Autor: | Cheng Chia-Hao, 鄭佳豪 |
|---|---|
| Rok vydání: | 2011 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 99 The research focus of this present thesis is put on K-band and V-band CMOS antennas, UWB bandpass filter, and K-band and V-band low noise amplifiers. The research topics include the five parts, as listed below. The first part is about the application of V-band wide-band on-chip antenna. The configuration of array antenna was used to meet the need of wide-band. The antenna chip was designed by TSMC 0.18μm CMOS process. The frequency range of this on-chip antenna is within 47.5GHz–85.5GHz, S11 is below -10dB and the bandwidth is 38.0GHz. The maximum of antenna power gain at 60 GHz is -6.52dB, and chip size is 1.33 mm2. The second part is about the application of 24/60GHz dual-band on-chip antenna. The configuration of meander antenna was used to fit in the requirement of dual-band. The antenna chip was designed by TSMC 0.18μm CMOS process. The frequency range of the on-chip is within 13.5GHz–26.5GHz and 40.5GHz–63.0GHz, S11 is below 10dB and the bandwidth is 13.0GHz and 22.5GHz. The maximum of antenna power gain at -21.8dB and -7.9dB, and chip size is 1.1 mm2. The third part is about the UWB low insertion-loss bandpass filter. The filter chip was designed by TSMC 0.18μm CMOS process. As for filter, the insertion-loss is 1dB at 4.2GHz, the frequency range of S11 and S22 is 2.4GHz–16.4GHz, and chip size is 0.221 mm2. The fourth part is about the K-band low noise amplifier. The LNA chip was designed by TSMC 0.18μm CMOS process. In order to have an increasing gain, the four common-source amplifiers were used. The second and the third stage were adopted to current-sharing technology to lower power consumption. This LNA achieved gain is at 13.39±1.47dB. The frequency of S11 is within 22.8GHz–50GHz below -10dB. The frequency of S22 is within 21GHz–27GHz below -8.65dB；The noise figure is 4.3-5.6dB; the power consumption is 22.2mW, and chip size is 0.72 mm2. Last part is about the V-band wide-band low noise amplifier which was designed by TSMC 0.09μm CMOS process. The low noise amplifier is the configuration of the third stage cascade amplifier. The common-source amplifier was used in the first stage. The second and the third stage were the combination of common-source amplifier and common-gate amplifier. The power gain of this amplifier is 16.78±1.43dB, the frequency of S11 and S22 at 55GHz–65GHz are below -19.25 and -14.56dB, the noise figure is 5.25-6.05dB, the power consumption is 29.1 mW, and chip size is 0.66 mm2. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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