Clock and switching power optimization with multi-bit flip-flops
| Autor: | Yao-Tsung Chang, 張耀宗 |
|---|---|
| Rok vydání: | 2011 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 99 Low power design methodology is more and more important in modern IC design because power consumption dominates other design objectives, such as area and timing, in modern system-on-chip (SOC) applications. High power dissipation may also have great impact on circuit lifetime and reliability due to higher chip thermal density. Applying multi-bit flip-flops (MBFFs) for clock power reduction has been becoming one of the developmental lower-power design techniques. In this thesis, we present a novel approach to save clock power by applying MBFFs. Our approach can simultaneously minimize both clock power and net switching power while considering the placement density and timing slack constraints. Experimental results based on the industrial benchmark circuits show that our approach can reduce clock power by 16.5% and net switching power by 14% within seconds. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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