The Design of All-Digital Delay-Locked Loop using Standard Cell Library
| Autor: | Ting-Li Chu, 朱庭立 |
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| Rok vydání: | 2010 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 98 In the thesis, an all-digital delay-locked loop (ADDLL) using ARM Cell-based Design Kit for TSMC 0.18um process provided by National Chip Implementation Center is presented to realize the clock deskew function. Unlike most of the ADDLL designs are based on Full-Custom Flow, this work is completely designed according to Cell-base IC Design Flow. The proposed all-digital delay-locked loop consists of a phase detector (PD), a successive approximation register-controller (SAR), an adaptive digital-controlled delay line (ADCDL), a time-to-digital converter (TDC) and the control unit which is composed by combinational logic circuits.In order to enhance the resolution of delay line, the fine ultra tune stage is designed inside the fine tune stage such that the Least Significant Bit (LSB) can be restricted within 3ps ~ 24.7ps. The working rang of deskew function is within 8 ~ 430MHz. The lock-in time are 18 reference clock cycles. And the phase error is within 4.4ps ~ 55.7ps. When the input reference clock is running at 400MHz, the power dissipation is 5.66mW with the core area equal to 0.026mm2. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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