Study of VLSI Architecture Design for Analog Universal Biquad Filters

Autor: Yi-Zhen Liao, 廖宜楨
Rok vydání: 2010
Druh dokumentu: 學位論文 ; thesis
Popis: 98
In this dissertation, active elements such as Differential Difference Current Conveyor (DDCC), Operational Transconductance Amplifier (OTA), and Fully Differential Second-generator Current Conveyor (FDCCII) are used to design five kinds of biquad filter. First, a voltage-mode (VM) circuit is designed by using three DDCCs, three OTAs and two capacitors. It can realize low-pass, high-pass, band-pass, band-reject and all-pass filters simultaneously. The operating frequency can be up to 500 KHz with power consumption of 23.69mW. The chip area of the analog filter is 0.916mm2. For the second design, the high input impedance voltage-mode biquad filter is presented, which employs one DDCC, two OTAs and two grounded capacitors. It can realize three kinds of filter response including low-pass, high-pass and band-pass filters from the same configuration. The power consumption is 83mW and the chip area is 0.822mm2. Both of the biquad filters have the same advantages such as low sensitivity, no requirements for component matching conditions, no floating effects and any resistors, also the operating frequency can be adjusted easily. The third filter design employs two DDCCs, two resistors and two capacitors. It can realize low-pass, high-pass, positive band-pass and negative band-pass filters simultaneously. The power dissipation is 229.7μW and the chip area is 0.79mm2. Besides having advantages of low sensitivity and no matching conditions, this design has further advantages such as having no floating effects and has simply architecture. The fourth design used only five OTAs and two capacitors for the mixed-mode biquad filter. It can realize the voltage, current, trans-conductance, and trans-resistance mode filter responses. The advantages of the circuit are low sensitivity, the parameters and are orthogonally adjustable and the grounded capacitors can reduce the floating effects. The power dissipation is 30.95mW and the chip area is 0.823mm2. The final design uses one FDCCII, two capacitors and two resistors for the voltage mode biquad filter. The filter with two inputs and four outputs can perform simultaneous realization of voltage-mode band-reject, high-pass, band-pass and low-pass filter signals from the four output terminals, respectively. On the other hand, it also can act as a universal voltage-mode filter with three inputs and a single output and can realize five generic voltage-mode filter signals without any inverting input voltage signal and component-matching conditions. The H-SPICE simulations of five filters are with TSMC 0.35μm CMOS 2P4M process and TSMC 0.18μm CMOS 1P6M technology process respectively and Matlab was used to compare the theoretical results with the simulation. Finally, most of filter circuits have been implemented and measured.
Databáze: Networked Digital Library of Theses & Dissertations