Highly Accurate Data Converter Based on Nonlinear Capacitors
| Autor: | Yu-Sheng Chou, 周祐生 |
|---|---|
| Rok vydání: | 2010 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 98 The possibility of utilizing nonlinear capacitors for data converters is explored in this thesis. Various technologies are invented to reduce the performance degradation caused by the nonliearity of capacitors. For digital-to-analog converter, a 10-bit quasi-passive cyclic structure is adopted. Even though the INL of converted voltage is seriously deteriorated by the nonlinearity of capacitors, the linearity is still preserved for the amount of output charges during the operations of charging and redistribution. Finally a charge-to-voltage converter is utilized to generate required output voltage with enough accuracy. The test chips were fabricated in a TSMC 2P4M 0.35 μm CMOS process. The operation frequency, DNL and INL are +0.88~-0.17 LSB and +0.49~-0.57 LSB, respectively, at frequency of 700 kHz. The chip area is 0.26 mm2 and the power consumption is 14.3 mW. For analog-to-digital converter, a 10-bit SAR structure is adopted. By limiting the operation range of MOS capacitors to their most linear region, the linearity of the proposed ADC can be enhanced significantly. The test chips were also fabricated in a TSMC 2P4M 0.35 μm process. The operational frequency and INL are 2.4 MHz and +1.16~-1.37 LSB, respectively. The chip area is 0.47 mm2 and the power consumption is 2.73 mW. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
| Externí odkaz: |
|